1. Field of the Invention
The present invention relates to a clock generator adapted to generate different dot clock signals correspondingly to formats, respectively, of more than one video signal, formatted differently from each other, an image displaying apparatus and method in which the clock generator is used.
2. Description of the Related Art
The video signal formats adopted for the purpose of image display include those used in the television systems, such as HDTV (high-definition television) system and NTSC (National Television Standards Committee) double-speed system, which can implement a high resolution of image display with more than 1000 horizontal scanning lines (525 to 625 scanning lines in the conventional TV systems).
The above HD signal and NTSC double-speed signal are video signals, respectively, formatted as shown in FIGS. 1 and 2, respectively. The HD signal has a total of 1125 vertical lines per frame as shown in FIG. 1, while the NTSC double-speed signal has a total of 1050 vertical lines per frame as shown in FIG. 2. The horizontal scanning frequency depends upon a total number of vertical lines per field and a vertical scanning frequency. So, when the vertical scanning frequency is 60 Hz, the horizontal scanning frequencies of the HD and NTSC double-speed signals are as follows:
For displaying images of different horizontal scanning frequencies, a deflection system is necessary for each of the different horizontal scanning frequencies. To cope with this problem, the number of vertical lines in the NTSC double-speed signal is increased up to 1125 as shown in FIG. 3 for the NTSC double-speed signal to have a horizontal scanning frequency of 33.75 kHz. Namely, whichever a video signal supplied for display is, HD signal or NTSC double-speed signal, it will be displayed on the assumption that it has a horizontal scanning frequency of 33.75 kHz. Note that an NTSC double-speed signal whose number of vertical scanning lines is increased as mentioned above will be referred to as xe2x80x9cmagnified NTSC double-speed signalxe2x80x9d hereinafter.
In the HD signal shown in FIG. 1, the ratio of 1920 effective horizontal pixels to the total of 2200 horizontal pixels (1920/2200) is approximately 0.87, while in the NTSC double-speed signal shown in FIG. 2, the ratio of 1440 effective horizontal pixels to the total of 1716 horizontal pixels is about 0.84. Since the ratio of the effective horizontal pixels to the total of horizontal pixels in the HD signal is larger than that of the effective horizontal pixels to the total of horizontal pixels in the NTSC double-speed signal, the effective horizontal pixels will occupy a larger part of the total of horizontal pixels in the HD signal than in the NTSC double-speed signal, which means that the retrace ratio for the HD signal is smaller than that for the NTSC double-speed signal.
The deflection system provided for the above-mentioned reason and adapted to operate correspondingly to the HD and NTSC double-speed signals, respectively, adds to the manufacturing costs of the TV set or image displaying apparatus because of the difference in retrace ratio between the HD and NTSC double-speed signals. To avoid such an additional cost, it has been proposed to increase the total number of horizontal pixels in the HD signal so that the retrace ratio for the HD signal is nearly the same as that for the NTSC double-speed signal.
The total of horizontal pixels in the HD signal, required for the above purpose, will count 2280 in number because 1920/total number of horizontal pixels is 0.84 as in the above. Thus, with the retrace ratio taken in consideration, a video signal is adopted which is formatted to include a total of 2280 horizontal pixels as shown in FIG. 4. The video signal formatted as shown in FIG. 4 will be referred to as xe2x80x9cmagnified-retrace HD horizontal signalxe2x80x9d hereinafter.
Thus, a TV set in which 33.75 kHz is fixed as the horizontal deflection frequency, will display images represented by an HD signal as shown in FIG. 1, magnified NTSC double-speed vertical signal as shown in FIG. 3 and a magnified-retrace HD horizontal signal as shown in FIG. 4, respectively.
Frequencies of dot clock signals necessary for the three different formats of the HD signal, magnified NTSC double-speed vertical signal and magnified-retrace HD horizontal signal, respectively, are as will be described below. In Table 1 below, xe2x80x9cdot clockxe2x80x9d is a signal having a frequency derived from multiplication of the horizontal scanning frequency by the total number of horizontal pixels.
Since the horizontal deflection frequency (33.75 kHz) of the magnified NTSC vertical signal is the same as that of the HD signal, a clock generator is used to generate a dot clock signal by multiplying a horizontal scanning frequency by a total number of horizontal pixels.
However, many of the conventional TV sets use the PLL circuit as shown in FIGS. 5A to 5C. In FIG. 5, the PLL circuit is generally indicated with a reference 100. To generate a dot clock signal for each of video signals formatted differently from each other, the PLL circuit designed as shown in FIG. 5 selects a frequency division ratio in a frequency divider 101 according to the video signal format. More particularly, in the PLL circuit 100, the frequency division ratio is changed to 2200 as shown in FIG. 5A to generate a dot clock signal for display of the HD signal as an image, to 1716 as shown in FIG. 5B to generate a dot clock signal for display of the magnified NTSC vertical signal, and to 2280 as shown in FIG. 5C to generate a dot clock signal for display of the magnified-retrace HD horizontal signal. For this changing of the frequency division ratio, a select signal is supplied from outside to the frequency divider 101.
Thus, for display of the HD signal, the PLL circuit 100 generates a dot clock signal of 74.25 MHz from the reference signal of 33.75 kHz. For display of the magnified NTSC vertical signal, the PLL circuit 100 generates a dot clock signal of 57.915 MHz from the reference signal. For display of the magnified-retrace HD horizontal signal, the PLL circuit 100 generates a dot clock signal of 76.95 MHz from the reference signal.
Since the frequency divider 101 in the PLL circuit 100 shown in FIG. 5 has a high frequency division ratio, however, a dot clock signal generated as in the above is likely to have many jitters. Also, in the PLL circuit 100, the reference signal supplied to a phase comparator 102 has a frequency as low as 33.75 kHz. Therefore, the PLL circuit 100 cannot generate a reference signal by a crystal oscillator. For generation of a stable reference signal of 33.75 kHz, a crystal oscillator is used to generate a signal of about 10 to 25 MHz, for example, in frequency and the signal is divided in frequency. Also the PLL circuit 100 is designed to generate a horizontal deflection frequency by further passing the dot clock signal through other frequency divider. The other frequency divider for generation of a signal having the horizontal deflection frequency has a frequency division ratio L which is determined based on a number of scanning lines in all horizontal directions.
Next, determination of a frequency division ratio N in the PLL circuit for each of three video signals having different formats such as the HD, magnified NTSC vertical signal and magnified-retrace horizontal signal, will be described below by way of example.
The total numbers of horizontal pixels in the formats of the magnified NTSC double-speed vertical signal, HD signal and magnified-retrace HD horizontal signal are 1717, 2200 and 2280, respectively. Each of these numbers is decomposed into prime factors as shown below:
1716=2*2*3*11*13xe2x80x83xe2x80x83(1)
2200=2*2*2*5*5*11xe2x80x83xe2x80x83(2)
2280=2*2*2*3*5*19xe2x80x83xe2x80x83(3)
In the PLL circuit, the frequency division ratio N will be any one of the above prime factor combinations (1) to (3).
To use the same oscillator in a PLL circuit to generate dot clock signals for display of the magnified NTSC vertical signal, HD signal and magnified-retrace HD horizontal signal, each of the expressions (1) to (3) is divided by a greatest common divisor to provide a frequency division ratio N. Thus, the frequency division ratio N for the magnified NTSC vertical signal is 3*11*13=429, that for the HD signal is 2*5*5*11=550, and that for the magnified-retrace HD horizontal signal is 2*3*5*19=570. FIG. 6 shows PLL circuits capable of providing frequency division ratios N for the above signals, respectively. The PLL circuit is generally indicated with a reference 110. The PLL circuits 110 are configured for the frequency division ratios N for the above signals, as shown in FIGS. 6A to 6C, respectively. The PLL circuits 110 shown in FIG. 6 have frequency division ratios L of 2200, 1716 and 2280 determined depending upon the number of vertical scanning lines and dot clock signals for the signal formats, respectively, to provide a horizontal deflection frequency of 33.75 kHz.
In the PLL circuits 110 shown in FIG. 6, however, the frequency division ratio used to generate a signal for supply to the phase comparator is still high and the reference signal supplied to the phase comparator is as low as 135 kHz, so that a dot clock signal thus generated will have many jitters. Therefore, the PLL circuit 110 shown in FIG. 6 is not advantageous when processing an HD signal for display of a high-definition image.
FIG. 7 shows PLL circuits designed to provide frequency division ratios N of less than 100 and in which the reference frequency for supply to the phase comparator is in MHz. The PLL circuit is generally indicated with a reference 120.
As shown in FIG. 7, the PLL circuit 120 provides a frequency division ratio N of 55 for the HD signal as in FIG. 7A, a frequency division ratio N of 39 for the magnified NTSC vertical signal as in FIG. 7B, and a frequency division ratio N of 57 for the magnified-retrace HD horizontal signal as shown in FIG. 7C, respectively. In the PLL circuit 120 shown in FIG. 7, the reference signal for generation of dot clock signals for the HD signal and magnified-retrace HD horizontal signal should have a frequency of 1.35 MHz, and that for generation of a dot clock signal for the magnified NTSC vertical signal should have a frequency of 1.485 MHz.
However, it is difficult to generate, by a common crystal oscillator, the frequency of 1.35 MHz for the reference signal from which the dot clock signal is generated for the HD signal and the frequency of 1.485 MHz for the reference signal from which the dot clock signal is generated for the magnified NTSC vertical signal. Two crystal oscillators are required for this purpose. Therefore, even if the frequency division ratio N is set low, the two crystal oscillators are necessary, which will add to the manufacturing costs for the image displaying apparatus.
Accordingly, the present invention has an object to overcome the above-mentioned drawbacks of the prior art by providing a clock generator adapted to generate jitter-less dot clock signals for video signals different in format from each other, an image displaying apparatus and method, in which the clock generator is used.
The above object can be attained by providing a clock generator adapted to different dot clock signals correspondingly to formats, respectively, of video signals to be displayed as images, comprising according to the present invention:
means for generating a reference signal;
a voltage controlling/generating means for generating a dot clock signal;
means for dividing the frequency of the dot clock signal supplied from the voltage controlling/generating means;
a phase comparison means for detecting a phase difference between the reference signal supplied from the reference signal generating means and a signal supplied from the frequency dividing means;
a frequency division ratio setting means for setting the frequency division ratio for the frequency dividing means to less than a quotient resulted from division of a total number of horizontal pixels in each of the video signals by a greatest common divisor of the total number of horizontal pixels in the video signal having one format and total number of horizontal pixels in the video signal having the other format; and
a frequency division ratio selecting means for selecting a frequency division ratio set by the frequency division ratio setting means correspondingly to a format of a video signal.
In the above clock generator, the frequency division ratio setting means for setting the frequency division ratio for the frequency dividing means to less than a quotient resulted from division of a total number of horizontal pixels in each of the video signals by a greatest common divisor of the total number of horizontal pixels in the video signal having one format and total number of horizontal pixels in the video signal having the other format, is used to generate a dot clock signal for a video signal by changing the number of horizontal pixels in an image represented by the video signal to set a necessary frequency division ratio for the video signal.
Also the above object can be attained by providing an image displaying apparatus to display an image using a video signal converted according to a dot clock signal generated at a frequency division ratio set to less than a quotient resulted from division of a total number of horizontal pixels in each of the video signals by a greatest common divisor of the total number of horizontal pixels in the video signal having one format and total number of horizontal pixels in the video signal having the other format.
Also the above object can be attained by providing an image displaying method in which an image is displayed using a video signal converted according to a dot clock signal generated at a frequency division ratio set to less than a quotient resulted from division of a total number of horizontal pixels in each of the video signals by a greatest common divisor of the total number of horizontal pixels in the video signal having one format and total number of horizontal pixels in the video signal having the other format.
These objects and other objects, features and advantages of the present intention will become more apparent from the following detailed description of the preferred embodiments of the present invention when taken in conjunction with the accompanying drawings.